ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration

About the role

ASIC RTL design for AWS Inferentia ML inference chips.

Requirements

• Bachelor's degree
• 3+ years design or architecture of systems

What you'll do

• implement SystemVerilog RTL
• microarchitecture analysis
• synthesis and timing-clean designs
• lint and CDC checks

Where this was posted

• Indeed

  last seen 19m ago
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