BS/MS in EE/CE or related field, hands-on RTL design in Verilog/SystemVerilog, familiarity with ModelSim/QuestaSim/Vivado/Quartus and synthesis flow, Linux proficiency, Python/C/C++ a plus, eagerness to apply AI tools and learn HFT.
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Tualatin, OR
$161,700 - $258,800
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