Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

About the role

Chip-level static timing analysis for AWS ML accelerator hardware.

Requirements

• static timing analysis for block and full-chip

What you'll do

• develop STA flows
• write timing constraints
• fix timing issues via ECOs
• automation scripts

Where this was posted

• Indeed

  last seen 19m ago
  View on Indeed